1. Field of the Invention
The present invention generally relates to an input/output line sharing apparatus of a semiconductor memory device, and more specifically, to an input/output line sharing apparatus of a semiconductor memory device wherein a data line signal and a test mode signal share a global input/output line, and an input/output line is shared between test mode signals.
2. Description of the Related Art
A global input/output line in a memory device is an important factor to determine the area of peripheral circuits.
Referring to FIG. 1, the number of global input/output lines in a DRAM is shown.
The number of global input/output lines is determined depending on an internal prefetch structure. If 16 input/output lines are required in a X16 structure of a SDRAM, a DDR1 that has a 2 bit prefetch structure requires 32 input/output lines, a DDR2 that has a 4 bit prefetch structure requires 64 input/output lines and a DDR3 that has a 8 bit prefetch structure requires 128 input/output lines.
In other words, the area of the global input/output lines is increased by twice as the product is changed into the DDR1, DDR2 and DDR3. As a result, the area of peripheral circuit units depends on the number of global input/output lines which increases for high-speed.
In order to improve reliability of a semiconductor device in the DRAM, a test mode operation is required with a normal read/write operation. As a package type of the DRAM becomes FBGA, the number of test mode circuits increases.
However, in the prior art, a data line signal and a test mode signal individually use different input/output lines, so that they require a lot of global input/output lines.